This was a vacuum tube computer developed by the University of Tokyo in 1959.
In 1951, a general-research group called "Electronic Computer Research" was formed at the University of Tokyo, with a science and technology research grant from the Ministry of Education. The group leader was Hideo Yamashita, and another participant in the group was Tokyo Shibaura Electric(TOSHIBA), which at that time had started research on logic circuits based on vacuum tubes and cathode ray tube memory devices. In the beginning, research was conducted jointly, with the main division being that the University of Tokyo developed software while TOSHIBA focused on hardware development and manufacturing. At the end of 1954, a prototype was delivered from TOSHIBA to the Engineering Research institute of the University of Tokyo. Adjustments, which began in the following year (1955), ran into trouble, and the company withdrew from the joint research in 1956 without seeing the project's completion. Subsequently, research was continued at the University of Tokyo, by a team centered around Ayao Amemiya, and comprised of Toru Motooka, Hiroshi Yamada, Eiichi Goto, Kenro Murata and Kisaburo Nakazawa. With work by this team, the machine was completed in 1959, and it was used in many research projects until operation was stopped in 1962.
TAC used 7,000 vacuum tubes and 3,000 diodes, and was a binary serial computer with the EDSAC instruction set. For instructions, it used a 17-bit short word, and for numerical values a 35-bit long word. Main memory capacity was 1,024 short words (512 long words). The system had the following features:
- The random access system, using 16 cathode ray tubes, was employed in the main memory unit, and this enabled high-speed memory write and read. At that time, the only random access machine was the 2-frequency memory (512 short words) of the parametron-based PC-1.
- A floating point arithmetic unit was provided in hardware, and close attention was paid to overflow in the calculation process.
- This machine was an early adopter of the index register, which was used for the first time in the EDSAC II. Designation was done using a B digit bit in the instruction word.