Nakazawa Kisaburo was born in 1932, graduated from the Department of Applied Physics, University of Tokyo in 1955, and at graduate course, joined the TAC project. The development of TAC(Tokyo Automatic Computer) was started from 1951 by Yamashita Hideo and Amemiya Ayao, and utilizing vacuum tubes for logic elements, cathode ray tubes for main memory, initially designed by Toshiba co. However, the original TAC machine built in 1954 was not able to reach in operation.

So, he and his instructor Murata Kenro of Univ. of Tokyo carried out overall redesign and reform the machine and brought into operation in Feb. 1959. This new TAC was serial logic machine with clock frequency 333 kHz, about 7,000 vacuum tubes and Ge-diode, main memory was realized with cathode ray tube RAM 512 words (35 bits/word), and featured with hardware floating point arithmetic of 5.28 ms multiplication. New TAC was used until 1962 for actual scientific and engineering computation, one of the remarkable computational accomplishments of TAC was the verification of automatic proof of mathematical theorem by mathematician group.

He received his M.Eng, in 1957, and D.Eng in 1960, and then, joined Hitachi Ltd.and was engaged mainly in development of general purpose large scale computers such as HITAC 5020,5020E/F system, those was high speed transistorized 18MHz clock, 32 bits /word base machine, and utilized passive electro-magnetic helical delay line cable for multiple general purpose registers architecture.

After that, He played the leading role to realize actual product systems with various advanced technology such as high speed LSI, virtual memory, cache memory, multi-processor system and super computer.

He had been professor of the Department of Electronics and Computer Science at University of Tsukuba from 1989 to 1996. At that period, he performed main role of development of the massively parallel computer system CP-PACS(Computational-Physics by Parallel Array Computer System), which realized for a time the world top speed of 614 GFLOPS, with 2,048 high speed super-scalar RISC processors enhanced by PVP-SW(Pseudo Vector Processor based on Slide Windowed Registers) feature, which empowered super-scalar RISC processor as if micro vector super computers. Since, He has been professor of University of Electro-Communications from 1996 to 1998, and then, was professor of Meisei University through 2003.

He died on January 25, 2013.