【Priority Scientific Research Project】 JUMP-1 Massively Parallel Computer

Research into the JUMP-1 continued from 1991 to 1995 with the goal of building a prototype of a massively parallel computer driven by high-performance processor and compiler technologies. The project (led by Tanaka Hidehiko) relied on grant-in-aid funding for priority scientific research projects from the Japan Science and Technology Agency. (After the priority scientific research project, the Parallel Distributed Computing Consortium (PDC) continued the project until March 2000.)

The scientific research in this project was broken down into five research teams. Team A researched massively parallel-oriented applications, Team B researched massively parallel declaration languages, Team C researched operating systems, and Team D researched hardware realizations. The hardware built by Team D was the JUMP-1. JUMP was the acronym of the project, named Joint University Massively Parallel Processing.

JUMP-1 consisted of 128 clusters. Each cluster had four SuperSPARC+ microprocessors (each with one megabyte of secondary cache memory), two main memory units (each with 64 megabytes of memory), two memory based processors, and multiple high-speed serial I/O links. The clusters were coupled with a hierarchal torus network.

Compiled from pp. 201 - 202, "The History of Japanese Computers", edited by the Special Committee for the History of Computing, IPSJ. Ohmsha, 2010.

JUMP-1 massively parallel computer