【NEC】 ACOS System 2000 Series

In February 1986, NEC announced a series of ultra-large general-purpose computers which were the largest and fastest in the world at the time -- the ACOS System 2000 Series. This series employed a range of LSI technology including: ultra high-speed logic LSI (CML) with 1,000 gates and a delay time per gate of 100 picoseconds, ultra high-speed high-integration logic LSI (CML) with 4,000 gates and a delay time per gate of 170 picoseconds, 16-kilobit ultra high-speed bipolar RAM with an access time of 3 nanoseconds, and 1-megabit DRAM. It also employed packaging technology to enable installation of a maximum of 42 LSIs on a 10-centimeter-square multi-layer ceramic substrate, and used a direct liquid cooling system which performed cooling with liquid instead of air (as in previous machines). It also employed innovations such as the pipeline system and the integrated array processor system. This approach made the series the largest and fastest in the world.

The series also achieved high availability by employing approaches such as independent processors specially designed for RAS, a wide range of automatic retry functions (for everything from input-output commands to firmware instructions), processor relief functions and dynamic reconfiguration functions. These systems had hot standby capability to enable automatic and instantaneous switching to a standby system when a problem occurred in a loosely coupled multiple processor system, and a fault tolerant capability to enable processing with a normal system even in a load distribution loosely coupled multiple processor system where multiple processors perform online processing simultaneously. This made it possible to build highly reliable systems.

Artificial intelligence (expert systems) was used to facilitate computer management and use, even by persons without specialized knowledge.

ACOS System 2000 Series Specifications
  2010 2020 2030 2040
Announcement date February 1986
Number of arithmetic processing units 1 2 3 4
Main memory capacity Max. 256MB Max. 256/512MB Max. 512MB
Cache memory EPU cache 128KB 256KB 384KB 512KB
System cache 512KB 512KB/1,024KB 1,024KB
Number of channels Max. 96 Max. 192
General data transfer capacity Max. 192MB/s Max. 384MB/s
CPU element Bipolar CML (water cooled)
Memory element 1Mbit DRAM

ACOS System 900/1000/2000/3900 Series technical advances
  S900 S1000 S2000 S3900
Announcement date April 1976 September 1980 February 1986 March 1991
Shipping date October 1978 November 1981 June 1987 February 1992
Logic elements Bipolar CML Bipolar CML Bipolar CML Bipolar CML
Gate delay 0.7ns/ gate 0.5ns/ gate 100ps/ gate 70ps/ gate
Components per chip 200 gates max. 200 gates max. 1,000 gates max. 20,000 gates max.
Memory elements 16Kbit MOS DRAM 64Kbit MOS DRAM 1Mbit MOS DRAM 1Mbit CMOS SRAM
Access time 500ns 150ns 120ns 35ns
LSI package 8×8cm 8×8cm 10×10cm 22.5×22.5cm
No. of logic elements 110 max. 60 max. 42 max. 100 max.
LSI packages / board 12 packages / board 4 packages / card,
37 cards max. / board
12 packages / board 2 packages / board
Cooling system Air cooled Air cooled Water cooled Water cooled

ACOS system 2000