In 1979, the research center of the Nippon Telegraph and Telephone Public Corporation (now NTT) began studying the 5E Series as the successor to the DIPS-11/5 Series, and a development plan was launched in August 1982 to raise the processing capacity of information processing system centers, achieve more flexible system configurations, and respond to the need for higher reliability brought on by the growing scale of systems in those centers. The main features were (1) achievement of a highly reliable system with large-scale highly expandable system configurations, (2) higher performance and improved cost performance, and (3) centralization, saving of labor, and automation in operation/maintenance.
More specifically, for feature (1), the Series achieved a practical composite system configuration for realizing inter-processor connection using a high-speed optic loop system. For feature (2), it used state-of-the-art hardware technology such as highly integrated, high-speed logic LSI, and 256-kbit memory elements, and it used a dyadic configuration for comprising processor units and a dyadic configuration x 2 equipment configuration. For feature (3), centralization, automation, and greater remote handling of operation and maintenance functions were achieved by adopting a system control processor and by using a control loop system that enabled functions such as power supply control and configuration control, regardless of the number of devices or their type.
The DIPS-11/5E Series was comprised of 4 models: the Model 5E, 15E, 25E, and 45E. Prototyping of the Model 25E and composite system was completed in September 1985. Prototyping was finished in March 1986 for the Model 15E, in the middle of 1986 for the 45E, and at the beginning of 1987 for the 5E. (Main Specifications of DIPS-11/5E Series)
The 5E Series was very advanced in achieving a practical composite configuration system for connecting and controlling multiple host processors (CPUs) and multiple communication control processors (FEP) using a high-speed optic loop with a speed of 100 Mbits/sec.
In addition, it also enabled practical implementation of the DIPS-11/5E Series CCP (DIPS CCP-IE, CCP-IIE) and the DIPS database processor (RINDA).
| Item | Model 5E | Model 15E | Model 25E | Model 45E | (Reference) DIPS-1 | |
|---|---|---|---|---|---|---|
| Performance (DIPS-11/10 ratio) | 4.5 | 9 | 10 | 20 | 0.7 | |
| System | Number of CPUs | 1 | 2 | 4 | 4 | |
| Maximum main memory capacity (MB) | 128 | 256 | 512 | 16 | ||
| Total number of channels | 16 | 32 | 128 | 16 | ||
| Processing unit (CPU) | Number of instructions | 220 | 160 | |||
| Local memory capacity (KB) | 32 | 64 | 128 | 8/16 | ||
| Buffer memory capacity (KB) | 256 | 512 | — | — | ||
| Main logic element (G/chip) | 2K ECL LSI | 2K ECL LSI | 300 ECL LSI | 3K ECL LSI | ECL SSI§CMSI | |
| Memory unit (MEM) | Control unit (MB) | 8 | 16 | 32 | 1 | |
| Control unit (MB) | 32 | 16/128 | 1 | |||
| Memory elements (B chip) | 1M DRAM | 256 SRAM | Magnetic core | |||
| Transmission unit (DCH) | Number of channel types | 6 | 4 | |||
| Maximum throughput (MB/S) | 70 | 96 | 100 | 384 | 12 | |
