【Oki Electric Industry】 OKITAC-5090H

The OKITAC5090H was completed in 1963. It was designed for larger size and more general applicability, with an architecture significantly different from the previous OKITAC5090 Series Models A-D and M. The primary design goal of this machine was the realization of a time sharing system (TSS). In addition it was based on binary arithmetic (42-bit words), had a magnetic core memory which was expandable up to a maximum of 16 Kword, a cycle time of 5µs, and 42-bit wide buses and computing elements. To realize a TSS, the system used fully parallel processing for logical operations, and this made it possible to complete a 42-bit operation in a single clock cycle (5µs). Interrupt capabilities were enhanced, and all input/output devices were controlled with channel units. Fifteen input/output devices could be connected to each channel unit, and parallel processing was possible. The main features which salesmen focused on at the time included: high arithmetic speed (due to use of high-speed magnetic core for the arithmetic control section), larger memory capacity, a carefully selected set of about 200 instructions with high-speed modification capability, rational interrupt features, memory lock-out, and a modular " building block" system. Ideas from Kyushu University and joint studies played a large role in these architecture innovations.

*For specifications of the OKITAC5090H Model, go here.