The development of the parametron device was announced by Eiich Goto in July 1954, and under the leadership of Muroga Saburo (who had just returned from studying at the University of Illinois), a project was initiated at the Electrical Communication Laboratories of Nippon Telegraph and Telephone Public Corporation to fabricate a practical computer employing the parallel arithmetic system. In March 1957, Japan's first parametron computer, the MUSASINO-1, was completed. With the project goal of achieving the same architecture as the ILLIAC 1 (to enable use of the huge ILLIAC library), Muroga Saburo was in charge of the logic design, Yamada Shigeharu was in charge of the memory unit, and Takashima Kensuke was in charge of the parametron elements and exciters. Approximately 5,400 parametrons were used in this computer, and its prototyping cost was ¥15 million at the time (Table: Main Specifications of Musasino-1).

The MUSASINO-1 was used for computation services within the laboratory, but because it was a hand-made prototype, there were many problems with the hardware, and a great deal of labor was devoted to maintenance and operations. For this reason, the commercial MUSASINO-1B was not completed until 1960. It had exactly the same logical configuration, but it used eyeglass-type parametrons, which had been developed for practical application in electronic exchanges. The same machine was later sold by Fuji Telecommunications Manufacturing (currently Fujitsu) as the mid-size FACOM 201 for scientific calculation.

MUSASINO-1Parametron boardMUSASINO-1B
MUSASINO-1 Main Specifications