NEC rolled out the SX-5 series of supercomputers worldwide in June 1998. The SX-5 series featured a maximum vector performance of 4 teraFLOPS (four trillion floating-point operations in one second). Each node was constructed with up to 16 CPUs with a highly efficient shared-memory architecture for easy parallel processing. The maximum peak performance of each node was 128 gigaFLOPS, and each node had a best-in-class maximum of 128 GB of shared memory. In the maximum configuration with 32 nodes connected by an ultra-high-speed switch, the system reached 4 teraFLOPS with an astounding 4 TB of memory. Each CPU had a maximum performance of 8 gigaFLOPS, four times the maximum performance of the SX-4 series, by using high-density ultra-fast CMOS LSIs, built with cutting-edge 0.25-micron design rules, and 64 Mbit synchronized DRAM.
|Single-node model||Multinode model|
|Max. number of nodes||1||32|
|Max. number of CPUs||16||512|
|Max. vector performance||128gigaFLOPS||4teraFLOPS|
|Max. main memory capacity||128GB||4096GB|
|Max. memory transfer speed||1024GB/s||32TB/s|