【NEC】 SX-3 Series

In April 1984, NEC announced the SX-3 Series of supercomputers, which were the fastest in the world at that time. The SX-3 Series employed state-of-the-art technology, such as ultra-LSI with 20,000 gates per chip and a delay time per gate of 70 picoseconds, and was the first Japanese-made machine to achieve a loosely coupled multiprocessor system in which up to a maximum of 4 arithmetic processors shared main memory. In this way, the system achieved the world's highest processing speed with a maximum vector operation performance of 1.37 gigaFLOPS (max.) with a single processor, and 22 gigaFLOPS (max.) with a multiprocessor.

The Series used ultra high-speed CML LSI, with 20,000 gates per chip and a delay time per gate of 70 picoseconds, and high-speed RAM which achieved single-chip integration of a 7,000-gate logic circuit and a memory circuit with a capacity of 40 kilobits and access time of 1.6 nanoseconds.

NEC developed a new LSI ultra high-density package enabling mounting of a maximum of 100 ultra high-speed LSI on a multi-layer wiring board employing a polyimide-based resin insulation coating (suitable for high-speed operation) and thin-film microwiring technology. This made it possible to achieve ultra high-density mounting with a maximum of 2 million gates per package.

SX-3 Series Main Specifications
  Model
11
Model
12
Model
14
Model
22
Model
24
Model
42
Model
44
Announcement date April 1989
Max vector operation performance
(GFLOPS)
1.37 2.75 5.5 11 22
Number of arithmetic processors 1 2 4
Vector operation pipelines 4 8 16 8 16 8 16
Scalar operation pipelines 1set
Max. main memory capacity 512MB 1GB 2GB
Number of channels Max. 256
Max. overall data transfer speed 1GB/s

SX-3SX-3 packageSX-3 package with a liquid cooling module