The EM-4 was so named because it was the fourth ETL machine, with ETL standing for Electrotechnical Laboratory. The EM-4 was a data flow parallel computer designed for symbolic computations and simulations that ran on 1,024 processors. It was prototyped at the Electrotechnical Laboratory between 1986 and 1990 by a team led by Sakai Shuichi and Kodama Yuetsu. The prototype reached a maximum performance of 1 GIPS and a network performance of 14.63 GBps. The EM-4 was developed by first examining architectures, designing and prototyping LSI chips, building an 80-processor prototype, and developing a C compiler. The end goal was to realize a high-speed, flexible network that could connect around 1,000 parallel computers and raise data flow efficiencies. One of the LSI chips the team developed was the EMC-R, a dedicated processor chip for data flows.
The design team re-examined new architectures for data flows based on experiences with past data flow machines, beginning with the SIGMA-1. The result was that the EM-4 used a hybrid architecture that combined a data flow architecture and a Von Neumann architecture. The EM-4 was 21-times faster than the CRAY/XMP and 94-times faster than the SUN Sparc-330. The experiences gained from the EM-4 were utilized in the later EM-X and RWC-1.
Compiled from pp.199, "The History of Japanese Computers", edited by the Special Committee for the History of Computing, IPSJ. Ohmsha, 2010.
