ADENA was a data parallel computer proposed by Nogi Tatsuo of Kyoto University's Department of Applied Mathematics and Physics. ADENA I was a prototype machine with 16 microprocessors built at the university between 1978 and 1983. ADENA II was a working machine with 256 processors developed in partnership with Mitsubishi Electric between 1984 and 1989. The chief aims of the ADENA project were to achieve highly efficient parallelism for two- and three-dimensional array data used in scientific and engineering simulations and to simplify the language declarations to create these simulations. The foundation of parallel computing is, for a given matrix aij, to alternate as needed and as appropriate row processes, which parallel process the serial processes with respect to i across j, and column processes, which parallel process the serial processes with respect to j across i.
On the ADENA I, the premise was one processing state where the row elements are placed in a one-dimensional Pi array of processors (paired with local memory) and another state where the respective column elements are in an identical Pj array. A two-dimensional buffer memory array Bij was provided to allow for alternating data editing of these two states. This arrangement allowed for Pi ⇔ Bij ⇔ Pj data editing (transfers) — i.e., perfect coupling. The ADENA II, however, possessed a two-dimensional array of processors and a three-dimensional buffer memory array, which permitted Pij ⇔ Bijk ⇔ Pjk data transfers. This arrangement parallel processed three-dimensional array data directly in three states — row processing, column processing, and pillar processing. It also involved quasi-perfect coupling, whereby data could be transferred between all processors in two transfers via one arbitrary processor. Because of this quasi-perfect coupling, the ADENA II could easily simulate the ADENA I's processing methodology. The developers also created ADETRAN, a programming language based on an extension to Fortran, to directly express these parallel-processing operations. The ADENA II machine had 256 custom-built 64-bit processors and two gigabytes of total memory, and reached an effective speed of one gigaFLOPS.
Compiled from pp. 192 and 193, "The History of Japanese Computers", edited by the Special Committee for the History of Computing, IPSJ. Ohmsha, 2010.