Starting around 1975, RIKEN (the Japanese Institute of Physical and Chemical Research) successfully derived the design formula for an electron beam convergence/deflection system using a numerical processing system which could run on general-purpose computers. With this as background, RIKEN studied the development of numerical processing systems capable of handling more complex problems, and they planned the FLATS Project, which aimed to build a practical numerical processing system centered on a high-performance computer dedicated to numerical processing. The project was budgeted in 1979, and implemented over 5 years (total budget: approx. ¥400 million). The FLATS computer was fabricated by Mitsui Engineering & Shipbuilding, based on a design by RIKEN. Fujitsu also contributed to the design.
Goto Eiichi, a professor at Tokyo University who was in charge of the information science laboratory and also a chief researcher at RIKEN, had at that time conceived of HLisp (which applied hashing to Lisp), and was concentrating on that research one day at Tokyo University. He thought of the idea of running REDUCE (a type of numerical processing) with HLisp. REDUCE was widely used by porting it to general-purpose machines in a form which would run under an included Slisp, but Goto put it well when he said: "Running REDUCE on general purpose machines is like scratching the bottom of your foot with your shoes on." It is said that the FLATS Project was inspired when Yoshida Tohru of the Patent Section heard Goto's remark, and asked the relevant departments to work on the problem.
FLATS was an acronym for "Formula, Lisp, Association, Tuple, Set", and indicated: the language for achieving higher speed, the processing system and the incorporated data structures in the developed numerical processing computer. The overall system was comprised of the FLATS main unit as the back-end processor, and a front end processor (SVP) for performing input/output and maintenance/operation management.
The main features of the FLATS system -- the various techniques used to increase speed -- included the following:
- Parallel hash search mechanism to enable high-speed processing
- Hash search mechanism for Lisp basic operation and condition judgment
- Individual cache memory for data to enable high-speed access
- Use of dedicated instructions for garbage collection
- Use of lookahead control to absorb the execution time of branch, call and return instructions into other instructions
- Checking of data types at execution time
- 3 ports for register memory, and 3 operand in CPU instructions
- Arithmetic/Logic mechanism for multiple-precision data
Hardware support for virtual memory, and region segmentation via software
The FLATS hardware was comprised of approx. 23,000 ECL logic elements, and approx. 11,000 MOS and TTL logic elements. These were mounted on approx. 2,000 printed circuit boards. The cabinet housing the printed circuit boards was 115cm x 70cm x 161cm in size, and could house up to 324 boards. FLATS was comprised of 7 cabinets like this. Power consumption was about 100KVA overall, and a forced air cooling system was used for cooling. The system had performance as good or better than general-purpose computers, whose basic element speed and clock were about 8 times faster, and showed the effectiveness of a LISP-dedicated architecture. Starting in 1986, the experience gained with FLATS was used in fabricating FLATS2 for the "GOTO Quantum Magneto Flux Logic Project".
Members under Goto, members from RIKEN such as Soma Takashi, and members from Tokyo University participated in the FLATS Project.
(Compiled from Soma, Takashi: "The FLATS Numerical Processing Computer", Information Processing, Vol. 43, No. 2, pp.123-124 (2002).)
