【Kobe University】 Kobe University LISP Machine

The aims of the Kobe University LISP machine prototype were: to conduct research on architectures for high-speed execution of LISP, to build a sufficiently high-performance computer in the laboratory using bit-slice TTL LSI, and to conduct research on techniques for implementing interpreters with microprogramming. The system name was FAST LISP, and the name of the computer was TAKITAC-7.

The theme of the research was decided in 1977, and early work (in the spring and summer of 1978) focused on design of a LISP interpreter suitable for implementation via microprogramming. Priority was placed on using a bit slice ALU and hardware stack. From the summer to the fall, the team worked on architecture design, circuit design and part procurement, and began soldering printed circuit boards starting in the fall. Fabrication progressed while testing operation of boards using the LSI-11 front end processor (made by DEC), and the system was completed on February 10, 1979. In the first week, almost all bugs were eliminated, and the system operated stably thereafter. Basic performance data was gathered for about one week. The development period was about 1 year, and the system subsequently operated for a few years for research purposes. Today it is preserved in non-working condition.

Taki Kazuo (a Master's candidate at the time) and Kaneda Yukio (an assistant professor in the Faculty of Engineering at the time) were among those who participated in the development of this machine.

This era was a time when high-performance TTL LSI was catching on in the market, and high-performance experimental machines were being built even in research laboratories, and the idea of implementing an entire interpreter for a LISP machine via microprogramming arose naturally due to the above trends. The system used sixteen 70nsec 4k-bit SRAM from Intel in the hardware stack to increase speed, but each of these chips cost ¥10,000, so they were handled like precious treasure. A delayed load mechanism (like that used in today's RISC CPUs) was implemented for main memory access, and the idea of executing an interpreter using a 56-bit wide microprogram was very similar to VLIW computing. The interpreter had a micro-instruction cycle of 300nsec, and exhibited speed performance on a par with LISP compilers implemented on the large general-purpose computers of the time. The architecture of the TAKITAC-7 was inherited by later machines -- the FACOM-α, and ELIS from NTT.

(Compiled from: Kaneda, Yukio, Kazuo Taki, Koichi Wada and Naoyuki Tamura, "The Kobe University LISP Machine and Prolog Machine", IPSJ Magazine [Joho Shori] , Vol. 43, No. 2, pp. 114-115 (2002).)