【Mitsubishi Electric and Oki Electric】COSMO Series Model 500

Mitsubishi Electric and Oki Electric announced the COSMO series Model 500 in 1975 as a lower model of the COSMO series Model 700. It was a small computer system that offered high cost-performance benefits — due to the high-performance firmware that implemented the Virtual Control Memory — and high reliability — thanks to using LSI technology for the CPU, auto error correction, and micro diagnostics that made use of the Virtual Control Memory.

A microprogram controlled the CPU. The microinstruction length was 32 bits, and the control memory that stored the microprogram was a combination of ROM and RAM (a writable control store (WCS)). The standard model came with a 3.5K-word ROM and a 0.5K-word WCS.

Using a proprietary addressing scheme called the Virtual Control Memory, the logical addresses of the microprogram, which was in the 8K-word control store space, were mapped to physical addresses in units of 512-word block. This scheme permitted the CPU to continue to operate when a permanent failure occurred in a specific ROM block by loading the block’s data from main memory to the WCS and mapping the logical addresses that had been mapped to the ROM block to the WCS. This scheme also made debugging easier when developing firmware by mapping the logical addresses of the ROM space where the firmware would be stored to the WCS and running the firmware’s program on the WCS.

Using a proprietary addressing scheme called the Virtual Control Memory, the logical addresses of the microprogram, which was in the 8K-word control store space, were mapped to physical addresses in units of 512-word block. This scheme permitted the CPU to continue to operate when a permanent failure occurred in a specific ROM block by loading the block’s data from main memory to the WCS and mapping the logical addresses that had been mapped to the ROM block to the WCS. This scheme also made debugging easier when developing firmware by mapping the logical addresses of the ROM space where the firmware would be stored to the WCS and running the firmware’s program on the WCS.

In terms of I/O processing units, the Model 500 had an internal disk file I/O processor (IFA: Integrated File Adapter), a high-speed I/O processor (SEL), a direct I/O processor (DIO), a multiplexer I/O processor (MPX), a communication control processor (ICA: Integrated Communication Adapter), and a direct memory access channel (DMA). These units were contained within the CPU and all, except the DMA, operated under the control of the CPU’s microprogram. This design simplified the I/O processor hardware and made micro diagnostics possible. However, to reduce the intervention time in the execution and processing of CPU operations, data transfers of the IFA and the high-speed I/O processor were controlled through cycle-stealing using hardwired logic.

In terms of I/O processing units, the Model 500 had an internal disk file I/O processor (IFA: Integrated File Adapter), a high-speed I/O processor (SEL), a direct I/O processor (DIO), a multiplexer I/O processor (MPX), a communication control processor (ICA: Integrated Communication Adapter), and a direct memory access channel (DMA). These units were contained within the CPU and all, except the DMA, operated under the control of the CPU’s microprogram. This design simplified the I/O processor hardware and made micro diagnostics possible. However, to reduce the intervention time in the execution and processing of CPU operations, data transfers of the IFA and the high-speed I/O processor were controlled through cycle-stealing using hardwired logic.

The Model 500’s operating system was the Universal Processing System (UPS) that supported five processing modes — batch processing, remote batch processing, transaction processing, real-time processing, and TSS processing. UPS was able to execute symbiont and spooling processes simultaneously、and eight user jobs in parallel.

The main specifications of the MELCOM COSMO series Model 500 are given below.