This mid-sized computer was completed in 1967 as an online, real-time system that could be used for computer control, data communications control, scientific and engineering calculations, as well as small time-sharing systems.
The MELCOM 9100 had four sets of general-purpose registers, with three registers per set, that could be used as accumulators, index registers, or base registers. It was possible to switch quickly between programs by specifying with a program status word the register set to be used.
Instruction operands used logical addresses. A two-stage translation method, using segmentation and dynamic relocation as shown in the figure below, converted logical addresses to physical addresses. Segmentation was provided so that users could share programs or data stored in main memory. Dynamic relocation was provided so that programs could be executed irrespective of where they were loaded in main memory. The most significant bit of the 16-bit logical address indicated the segment. The value in the mapping register corresponding to the indicated segment was added to the logical address to find the physical address. Pages consisted of 512 words each. Main memory was protected with a two-bit memory lock code for each page.
Figure: Address translation processThe I/O processors had a repertoire of selector channel, a multiplexer channel, and a direct control channel. The I/O processors connected to I/O devices through the corresponding I/O controller. The selector channel was used for I/O operations with magnetic disks, magnetic drums, magnetic tape units, high-speed line printers, and similar devices. It had a maximum transfer speed of 440 kilobytes per second. Up to four selector channels could be mounted. The multiplexer channel was used for I/O operations with low-speed I/O devices such as paper tape readers and typewriters. It could be configured to have as many as 64 sub-channels, and it had a maximum transfer speed of 40 kilobytes per second. The direct-control channel was used with process I/O operations. Of the three channel types, the multiplexer channel shared CPU registers and adders and its data transfer operations were carried out by interrupting the CPU’s instruction processing.
The main specifications of the MELCOM 9100 series are given below.
| Main memory |
Technology |
Magnetic core |
| Capacity |
4K words – 64K words |
| Memory modules |
4K-word, 8K-word, 16K-word (up to four modules could be used) |
| Word length |
16 bits + 1 parity bit |
| Cycle time |
0.8 μs |
| CPU |
Data formats |
Fixed-point binary numbers (word, double word) |
| Variable-length decimal numbers (1 to 16 bytes) |
| Floating-point numbers (single precision: 32 bits, double precision: 64 bits) |
| Logical numbers (byte, word, double word) |
| Variable-length characters (1 to 256 bytes) |
| Instruction word length |
1 word, 2 words, 3 words, 4 words |
| Instruction types |
64 basic instruction types |
| Addressing |
Immediate, direct, indirect, based, relative, indexed |
| Types of operations |
Between registers, between a register and a memory location, between memory locations |
| Computation speeds |
Addition (between registers) |
1.4μs |
| Addition (between a register and a memory location) |
2.5μs |
| Multiplication |
8.4μs |
| Division |
11.2μs |
