Hitachi announced the MP5800 processor as the successor to the M-880 in April 1995 and began shipping models in October 1995. Hitachi developed a new super-fast, highly integrated, low-power LSI topology called advanced CMOS-ECL (ACE), which united high-speed bipolar ECL and highly integrated CMOS circuitry. From this development, Hitachi built logic LSIs with 120,000 gates and 40 ps latency and internal logic RAM LSIs as large as 2.3 megabits with access times of 1 ns. By placing these circuits in high-density modules, Hitachi created the instruction processor in a module one-tenth the size of that on the M-880. This integration doubled the processing power of the previous model and allowed the new models to accept up to eight processors.
Hitachi also developed a new compact, high-efficiency power supply with a DC-DC convertor methodology. These innovations dramatically reduced the installation space and power consumption per unit performance to between one-fourth and one-sixth compared with the M-880.
| 180,210,310,410 | 220,320,420,520,620,720,820 | |
|---|---|---|
| No. of instruction processors | 1-4 | 1-8 |
| Main memory capacity | 256MB-2GB | 512MB-2GB |
| Extended memory capacity | 0-4GB | 0-8GB |
| No. of channels | 16-128 | 32-256 |
Hitachi announced the MP5600 processor as the successor to the M-860 in April 1996 and began shipping models in September 1996. With about double the performance of the M-860 and a multiprocessor architecture that could be expanded to as many as eight processors, the MP5600 processor series consisted of 12 models covering a range of about 18 times in performance capability. CMOS LSI technology was used exclusively, and CMOS LSI chips with up to 600,000 gates were used for main memory, extended memory, and I/O processors. The MP5600 processors were one-box systems that took up to 85 percent less space and used up to 90 percent less energy than the M-860. By adding the H-6710 high-speed coupling device, scalable systems could be created that supported parallel processing functions between as many as 32 central processing nodes (a CPU formed from multiple tightly-coupled processors).
Hitachi announced the MP5500 processor, a smaller line under the MP5600, along with the MP5800 in April 1995 and started shipping models in October 1995. MP5500 processors were standard equipped with a data-compression mechanism, Advanced Connection Architecture (ACONARC) — a channel-path sharing function that made it possible to connect optical fiber, and an I/O dynamic reconfiguration function.
The MP5400 processor was a core server for small and medium-sized systems that provided support for open systems while continuing to utilize M series resources. Hitachi announced the MP5400 processor in September 1995 and started shipping units in December 1995. The MP5400’s three biggest features were an RDB parallel architecture, which processed relational databases in parallel to basically double the total throughput of core business processes; an open-system parallel architecture, which processed mainframe tasks and open system tasks in parallel; and the Open Job Way function, which automated task connections between mainframes and open systems using UNIX or Windows NT.
