The ETL Mark V transistor computer was developed in May 1960 at the Electrotechnical Laboratory. This machine was planned in 1958, based on results obtained with the ETL Mark IV, as a decimal floating point computer, and was designed to meet the need for scientific and engineering computation within the Electrotechnical Laboratory. The system and logic design was conducted primarily by Aiso Hideo (ETL Electronics Division), with the help of others including Yaita Tetsu (also of the ETL Electronics Division), Kitagawa Setsu (a research student at Keio University, Faculty of Engineering), and Tsuzuki Togo (a graduate student at Keio University, Faculty of Engineering). The machine was fabricated by Hitachi. It had a clock frequency of 230KHz, a magnetic drum with 4,000 word capacity as a memory unit, and could execute about 150 types of instructions. The Mark V was the prototype of the HITAC 102, which was later commercialized by Hitachi. When they returned to Keio University, Kitagawa and Tsuzuki fabricated the KCC based on the design of the Mark V, and provided it for use within the University.