Keio University Transistor Computer K-1

Keio University developed the transistor computer K-1 in 1958 as a part of the project celebrating the university's centennial anniversary. Based on ETL Mark IV transistor computer of the Electrnotechnical Laboratory (ETL), they developed a fully transistorized machine. To meet the need for scientific and engineering computation, a floating point arithmetic unit and index registers were introduced. They adopted dynamic circuits for basic circuits. The clock was synchronous and the rate was 200kHz.

Internally, the K-1 was decimal-based and used the bit-parallel/digit-serial system. The word length was expanded from 6 digits to 12 digits. A high speed magnetic drum was used as an internal memory. As for input/output devices, a mechanical tape reader, a Flexowriter, and a paper tape punch were used.

Misao Kitagawa and Togo Tsuzuki of Faculty of Engineering engaged in the design work of ETL Mark V at ETL and studied the practical work of computer design. After finishing the study at ETL, they returned to Keio University in July 1958 and started to design the K-1 transistor computer. From November 1958, Kitagawa, Tsuzuki and the students of the laboratory began to fabricate the K-1 and then tested the machine. The machine test was completed in June 1959 and the K-1 began to operate.　Thus the first Japanese university made transistor computer was born.

In July 1961, the computer center was established within the Faculty of Engineering, K-1 was installed there and was used until 1968 for the research and education within the campus.

Currently the central processing unit (CPU) of K-1 and a magnetic drum are preserved in Yagami Campus of Keio University. The CPU is exhibited in the basement of 11th Building and the drum is in the basement of 14th Building.