HITAC 8700

In 1967, a national project to develop ultra high-performance electronic computers was initiated, and Hitachi was asked to play the central role. This project brought together the best of Japanese domestic technology. Academia, government and industry provided support and cooperation, and related parties gave their best effort. The machine was completed in 1972.

The HITAC 8700 was developed commercially by using the technological results of this project. It features Japan's first 32-bit virtual addressing architecture, multi-processors sharing main memory, a buffer memory system, and an advanced memory protection mechanism. Performance was at the top level in the world at that time.

It employed IC composed of an average of three gates and LSI composed of an average of 30 gates. The operating time was 1.5 nanoseconds per gate.

It achieved higher reliability by retrying an instruction when an error occurred in its execution, correcting an error automatically when it occurred during a memory read, and testing to detect a failure part.

Instructions and arithmetic operations were controlled by microcode stored in a high-speed wire memory. Some processes which were used frequently were implemented by firmware. This enabled those processes to be executed two to three times faster.

The first machine was delivered to the Tokai Bank in May 1972. HITAC 8700 was adopted in the Japanese National Railways seat reservation system (MARS 105), and used for a wide range of applications such as large-scale online systems, bulk batch processing systems, and timesharing systems which were used simultaneously by a lot of users.