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DIPS-1 System Components (CPU board, etc.)
| Manufactured in | 1971 |
|---|---|
| Manufactured by | Nippon Telegraph and Telephone Public Corporation (Nippon Telegraph and Telephone Corporation) |
| Owner | Nippon Telegraph and Telephone Corporation |
| Location of historical materials | 3-9-11 Midori-cho, Musashino-shi, Tokyo, 180-8585 NTT History Center of Technologies (NTT Musashino Research and Development Center) |
| Visitor information | Open to the public |
| Contact | NTT History Center of Technologies Tel.+81-422-59-2093
https://hct.lab.gvm-jp.groupis-ex.ntt/english/contact.html |
In 1967, the DIPS Project was launched, and from the latter half of 1968 started the actual development activities of the DIPS-1 System. The goal of the project was set to accomplish the development of the information processing systems for the large scale data communications by March 1973, both in hardware and software, and to ensure that system could overtake the most advanced competitors at the time in terms of system performance and performance/cost ratio. In April 1969, the joint research project was established with members of NEC, Hitachi and Fujitsu under the leadership of the Electrical Communication Laboratories of Nippon Telegraph and Telephone Public Corporation.
The DIPS-1 system adopted the cutting-edge technologies at the time, with max. 4 multi-processors, local memory modules (cache) using NMOS-ICs, virtual addressing with paging, and main memory modules with max.16 MB. To achieve the software compatibilities within the series of machines for the DIPS-1, the architecture was standardized in machine language level (i.e. command/instruction) and the I/O interface specifications were also standardized for ensuring the peripheral device compatibility for the system families.
In October 1971, the prototype development was accomplished, and in March 1972 the field test-bed system (DIPS-1F) was installed in the Shiba Subscriber Exchange Office in Tokyo. Many DIPS-1 systems were adopted in scientific/engineering computation services (e.g. DEMOS-E) and banking systems.
Only several system boards are extant for DIPS-1 in NTT History Center of Technologies,
⁻ DIPS-1 CPU Logic Package (3 items)
⁻ DIPS-1 CPU Local Memory Package
⁻ DIPS-1 CPU Logic LSI
⁻ DIPS-1 Main Storage Core Memory
⁻ DIPS-1 Channel Unit Package
The DIPS-1 system adopted the cutting-edge technologies at the time, with max. 4 multi-processors, local memory modules (cache) using NMOS-ICs, virtual addressing with paging, and main memory modules with max.16 MB. To achieve the software compatibilities within the series of machines for the DIPS-1, the architecture was standardized in machine language level (i.e. command/instruction) and the I/O interface specifications were also standardized for ensuring the peripheral device compatibility for the system families.
In October 1971, the prototype development was accomplished, and in March 1972 the field test-bed system (DIPS-1F) was installed in the Shiba Subscriber Exchange Office in Tokyo. Many DIPS-1 systems were adopted in scientific/engineering computation services (e.g. DEMOS-E) and banking systems.
Only several system boards are extant for DIPS-1 in NTT History Center of Technologies,
⁻ DIPS-1 CPU Logic Package (3 items)
⁻ DIPS-1 CPU Local Memory Package
⁻ DIPS-1 CPU Logic LSI
⁻ DIPS-1 Main Storage Core Memory
⁻ DIPS-1 Channel Unit Package
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